Ultra-low-power (ULP) transceivers enable short-range networks of autonomous sensor nodes for wireless personal area network (WPAN) applications, such as Bluetooth® Smart and Zigbee®. RF phase-locked-loops (PLLs) for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ULP WPAN radios. Compared to analog PLLs, all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they offer benefit from smaller area overhead, programmability, capability of extensive self-calibrations, and easy portability. However, analog PLLs currently still dominate the field of ULP WPAN radios, since the time-to-digital converter (TDC) of an ADPLL has traditionally been power hungry.
An example approach for minimizing the power consumption of a TDC circuit in the ADPLL is to reduce the activity of the TDC so that it operates only within a predetermined observation window. Such a TDC is known from J. Zhuang, et al., “A Low-Power All-Digital PLL Architecture Based on Phase Prediction,” ICECS, 2012, where a 2.1-2.7 GHz fractional-N ADPLL for WPAN applications digital-to-time converter (DTC)-assisted snapshot TDC is presented. In this implementation TDC snapshotting is implemented to reduce the sampling rate of the TDC from FCKVD2 (output variable clock (CKV)) to FREF (frequency reference (FREF) clock). A DTC is provided for reducing the detection range of the TDC detection range to less than 1/10 of the digitally-controlled oscillator (DCO) output signal period, leading to a significant power reduction. The accumulated fractional part of the frequency command word, FCwfrac, controls the DTC to delay the reference signal FREF such that the delayed reference clock FREFdly is almost aligned with CKVD2 (CKV clock divided by 2), once the loop is locked. FREFdly also triggers the snapshot to catch the first CKVD2 edge so that only one CKVD2 edge, CKVD2S, per reference period is fed to the TDC. By capturing only one edge, the snapshot technique guarantees that the TDC has the minimum activity and consume minimum power. Moreover, the snapshotting also minimize the supply switch noise during TDC operation.
A reduced-range TDC operating at the reference frequency (32 MHz) then compares the edge of CKVD2S with FREFdly to provide the fractional phase error, PHEF. This approach reduces both sampling speed and detection range of TDC, leading to around 200× power reduction. In the snapshot TDC, the narrow observation window is opened by the CKVD2s, which acts as a TDC enable signal, after the rising edge of FREFdly. Since the TDC captures only the first rising edge of the variable clock, CDVD2, after the rising edge of FREFdly, the timing of opening TDC observation window is critical. In order to compensate for the delay added by the snapshot circuit, a TDC “offset delay” (T1) is added between the rising edge of FREFdly and the TDC observation window. However, the TDC and snapshot circuit offset delays cannot be easily estimated due to parasitic or slow logic transitions introduced in the layout during the design phase or during operation. As a result, due to the mismatch between the TDC and snapshot offset delays the TDC may be activated outside of the predetermined observation window, thereby causing the TDC to generate an erroneous output code, resulting in the degradation of the overall PLL performance, e.g. by introducing unwanted phase noise, and sometimes may even lead to an unstable PLL locking.